THE ULTIMATE COMPUTER ===================== (C) David A.S.Crofts 1998 OVERVIEW -------- - Please refer to Fig. 1. - The key to the computer is : - a set of PINS - a PIN ADDRESS BUS - a FUNCTION CODE BUS - a CONDITION CODE BUS - a DATA BUS - All PIN except CONDITION CODE PIN can be referenced by PIN ADDRESSES. - All PIN except the OPEN DATA REGISTER TO ANSWER BUS PIN have a PIN ADDRESS REGISTER. - When a PIN ADDRESS is placed on the PIN ADDRESS BUS it will ACTIVATE the PIN it refers to. - When CONDITION CODE BUS LINE n is set by the DATA PROCESSING UNIT it will ACTIVATE CONDITION CODE PIN n. - Each DATA REGISTER has an arbitary number of FUNCTION CODE REGISTER. - When a PIN ACTIVATES it will perform its DESIGN ACTION. PIN and their DESIGN ACTION --------------------------- - SEND FUNCTION CODE AND DATA PIN : - The contents of the FUNCTION CODE REGISTER is sent along the FUNCTION BUS. - The contents of the DATA REGISTER is sent along on the DATA BUS. - The contents of the PIN ADDRESS REGISTER for this PIN is placed on the PIN ADDRESS BUS. - OPEN DATA REGISTER TO ANSWER BUS PIN : - The DATA REGISTER opens to the ANSWER BUS. - The CONDITION CODE PINS for this DATA REGISTER open to the CONDITION CODE BUS. - CONDITION CODE PIN n : - The contents of the PIN ADDRESS REGISTER for this PIN is placed on the PIN ADDRESS BUS. DATA PROCESSING UNIT EXPECTATIONS AND ACTIONS --------------------------------------------- - When an ANSWER is sent it is assumed that control will continue because an OPEN DATA REGISTER TO ANSWER BUS PIN has been ACTIVATED hence selecting its CONDITION CODE PINS. - The DATA PROCESSING UNIT will only ACTIVATE one CONDITION CODE PIN. REASONABLE LIMITS FOR A REAL COMPUTER ------------------------------------- - There should reasonably be 2 FUNCTION CODE REGISTERS per DATA REGISTER. - 3 CONDITION CODE REGISTERS would probably suffice. CC1 = LESS THAN ZERO, CC2 = ZERO, CC3 = GREATER THAN ZERO. IMPLEMENTATION OF FLAT INSTRUCTIONS ----------------------------------- - Please refer to Fig. 2. - Each PIN ADDRESS should be divided into 2 parts. |----------------------------|--------------------| | FLAT INSTRUCTION ADDRESS | REAL PIN ADDRESS | |----------------------------|--------------------| - FLAT INSTRUCTION ADDRESS of NULL means the current FLAT INSTRUCTION. - When a new FLAT INSTRUCTION is LOADED all REGISTERS are new except the DATA REGISTERS. OBSERVATIONS ------------ - It would be good if you could LOAD a FLAT INSTRUCTION with one operation, so a VERY WIDE bus is required. If you can't there are various ways to implement FLAT INSTRUCTIONS and still have a fast computer. - With a wide FUNCTION CODE you can implement very obsqure functions. - Please refer to example programs. - After writing example programs I found the following : - You might get by with only 1 DATA REGISTER but you still need descrete CONDITION CODE REGISTERS. Therefore the DATA REGISTER could be in the DATA PROCESSING UNIT and you don't need the DATA BUS. - There are many times when all CCn PIN ADDRESS REGISTER are the same, so it would be good if you could make the PIN ADDRESS REGISTER as small as possible. Therefore you could have the PIN ADDRESS REGISTER perform BRANCH SHORT (perhaps only within the current FLAT INSTRUCTION) and have a FUNCTION CODE for BRANCH LONG. - You could have a FUNCTION CODE, GO_360(program), to execute 360 machine code but the prefered option would be to recompile PLI or COBOL into FLAT INSTRUCTIONS. - The DATA PROCESSOR RAM used for static and automatic data should be a different memory subsystem to the FLAT INSTRUCTION RAM. - I will leave it to the reader to implement :- - ADDRESS SPACES - LINKING and LOADING - INTERUPT HARDWARE - SVC's - DATA PROCESSING UNIT I/O SUBSYSTEM |